Non-volatile semiconductor memories, i.e. those that do not lose data when the electrical power is interrupted, have been available for many years. Many NVRAM cells employ a programmable threshold voltage device as a non-volatile (NV) element for non-volatile data retention and a bistable multivibrator or flip flop as a static random access memory (SRAM) element for volatile data read and write operations. The programmable threshold voltage device usually does not function during normal volatile operation since the flip flop performs the data retention, read and write functions so long as electrical power is available. Before power is interrupted, or at the time when the interruption has been detected but has not yet taken effect, the programmable threshold voltage device is "programmed" to retain the data then present in the flip flop. In this manner the volatile data contained in the flip flop is not lost, but is retained by the programmable threshold voltage devices. Non-volatile semiconductor memories thus offer the long term data retentive characteristics of other types of computer memories, such as magnetic media, but offer considerably more convenience of use.
Examples of known programmable threshold voltage devices are metal nitride oxide semiconductor (MNOS) field effect transistors (FETs), silicon nitride oxide semiconductor (SNOS) transistors, silicon oxide nitride oxide semiconductor (SONOS) transistors and floating gate semiconductor transistors. All of these programmable devices have the common characteristic of being able to store an electrical charge for a long period of time within an internal structure between a silicon surface and a control gate. The stored charge programs the device, so that when the power is restored, the stored charge modifies the threshold voltage of the device and the resulting electrical characteristics. The programmed characteristics set the flip flop in a state which relates to the state of the flip flop just prior to the programming operation.
Each of the above mentioned programmable threshold voltage devices exhibits a finite lifetime of program/erase cycles (an "erase" occurring before the "program"), before the device loses its ability to reliably store a charge. Since the typical flip flop or SRAM may be set and cleared many times during normal computer operations, the finite lifetime of the programmable devices would be quickly reached if programmable devices were incorporated in the flip flop or SRAM portion of a NVRAM. Additionally, programming the programmable devices usually requires a relatively high voltage and a relatively long time to program the device, which would make the set and clear operations very slow during normal computer operations. It is for these reasons that the programmable devices are typically separate from the flip flop in the NVRAM cell circuit.
One of the primary considerations in the design of any semiconductor memory is the ability to produce as many memory cells on a semiconductor chip as possible. More memory cells per unit area of chip are desirable because the cost per unit of memory decreases, and a greater amount of memory is usually desirable in modern computers. The cost of manufacturing a semiconductor chip is generally governed by its area and not by the number of components it incorporates, so integrating more components on the chip does not increase the manufacturing cost in a theoretical sense. Accordingly much effort is devoted to reducing the number of components in a semiconductor circuit and laying out or arranging the components in a space efficient manner. Space economy is particularly important because the memory cell will be replicated many thousands of times in a single memory chip. Furthermore, if the circuitry of the cell itself can be arranged to minimize the number of components while still accomplishing the non-volatile and SRAM functions and to reduce the spacing between the components, the cell design will be more efficient.
The typical approach of combining a programmable device with a flip flop in an NVRAM cell is to connect one programmable device to each of the two data output nodes (true and complement) of the flip flop. The programmable threshold voltage devices usually function in one of two modes in such circumstances: either as capacitors, where the storage of charge establishes a differential in capacitance in the two devices as a result of the signal levels at the data output nodes at the time of programming; or as programmed current switches, where the stored charge modifies the threshold voltage at which the devices commence conducting current when the programmed data is recalled to the flip flop.
The capacitance approach, while providing some reduction of cell size through conservation of components, has the unfortunate characteristic of creating a data inversion when the programmed data is transferred to the flip flop. Another disadvantage is that the relative capacitance differential over time tends to diminish. A diminished relative capacitance greatly increases the risks of incorrectly setting the state of the flip flop during recall. The cell disclosed in U.S. Pat. No. 4,271,487 is an example of a differential capacitance approach.
The programmed current switch approach, while providing a more affirmative setting of the flip flop even after the passage of significant time, has had the disadvantage of requiring more space consuming components to operatively separate the non-volatile elements from the SRAM (flip flop) elements during normal operation. The cell disclosed in U.S. Pat. No. 3,636,530 is an example of a prior art current switch approach.
An important space consideration in the layout of memory cells involving programmable threshold voltage devices is that increased spacing must be provided to withstand the relative high voltages required for programming the programmable devices, to withstand the high voltage without breaking down the insulation and detrimentally affecting the other components or the circuit operation. If the circuit design of the cell requires the high voltage to be present at many different locations and on many different components, wider spacings and longer channel lengths are required. These requirements consume extra space, increase the size of the cell, and result in lower integration density and poorer chip performance.
Of course, another important consideration is minimizing the number of manufacturing steps necessary to produce the semiconductor memory chip. The various transistors, resistors and other elements are generally formed with layers upward from a silicon substrate. The layers, and the configuration of the components, are formed in separate process steps. If the layout of the circuit can be arranged to minimize the number of layers and connections between layers, a reduced number of process steps are required. By minimizing the number of process steps, the opportunities for errors or problems are reduced, while an overall reduction in the price of fabricating the semiconductor memory chip is achieved.
It is against this background of various considerations, and others, that the present invention has evolved.